1. Field of the Invention
The present invention relates to a semiconductor device including several means for suppressing and controlling a temperature increase caused by excessive consumption of electric power in the integrating semiconductor devices below the allowable maximum temperature with less sacrifice of performance.
2. Description of the Prior Art
Generally, power consumption generated from one semiconductor element is far less than that from one electronic tube and the like device. Accordingly, in a case of semiconductor devices of relatively small integration, heat generation or temperature increase caused by operation of such devices is usually small. Therefore, it is not necessary to provide such devices with special means for temperature control.
Moreover, with the recent increase of the integration degree in semiconductor devices such as LSI, IC, the power consumption per one semiconductor element has been greatly reduced, and such tendency will be more remarkable. To the contrary, the power consumption per unit area of highly integrated semiconductor devices is increased because the number of semiconductor elements included in the devices is remarkably increased in spite of reduction in size of the devices.
Particularly, fine-processing technology for producing memory devices is now well advanced. Therefore, the memory capacity has been rapidly increased from 1M bits to 64M bits. Moreover, the elevation of the integration degree of such memory devices is eagerly required and studied in the semiconductor field.
Accordingly, it is necessary and will be more necessary to provide semiconductor devices with special means for controlling temperature increase due to the improvement of the integrated density. By the way, power consumption Pw per unit time to be generated in a semiconductor device can be generally expressed by the following formula: EQU Pw=K.multidot.C.multidot.V.sup.2 .multidot.fc (1)
where V is operating voltage, fc is a driving clock frequency, C is total capacitance of the semiconductor device , and K is a constant number under a condition that the capacitance C is fully charged and discaharged.
The operating voltage V, in the equation (1), is ordinarily determined in advance due to a property of a semiconductor element to be used. Therefore, it is very difficult to change the supplied voltage to the semiconductor device from the outside during the operation thereof.
Accordingly, such a method of changing the operating voltage V during the operation has actually never been tried so far.
Hereinafter, a conventional technology will be explained from three points of view.
Firstly, a method concerning the clock frequency will be explained. In a conventional technology, a clock frequency is so selected as to be constant and to restrain the temperature increase of a semiconductor device within an allowable range. Then, a constant and lower clock frequency fc is adopted for operating during all operating period.
According to such a method, however, it is difficult to sufficiently utilize operational characteristics corresponding to a high-frequency range or correctly execute high-speed operation or process, in some specific parts of the semiconductor device.
Secondly, a method concerning the total capacitance C of each semiconductor will be described as follows.
Generally, the capacitance of a semiconductor device such as a LSI consists of capacitance in the semiconductor elements and capacitance in the parasitic capacitance.
For example, in a MOS element, the element capacitance consists of the MOS capacitance and the junction capacitance. In this case, the element capacitance per one semiconductor element is reduced with an increase of the integration. However, since the number of the elements per one semiconductor device is increased at the same time, the total element capacitance is not greatly changed by the increase of integration.
On the other hand, the parasitic capacitance is so-called stray capacitance in the wiring portion, and consists of capacitance generated between adjacent wiring lines and capacitance generated between each wiring line and the substrate.
When the integration degree of a semiconductor is increased, the width of each wiring line is narrowed in inverse proportion to the increase of the number of wiring lines. Therefore, the total area of the portions where the wiring lines face to the substrate is not changed so much. Moreover the thickness of the insulating layer is decided regardless of the integration density. Accordingly, the capacitance generated between the wiring lines and the substrate is not changed by the change in integration density.
On the other hand, since the distance between the wiring lines is decreased as the integration density increases, the capacitance between each adjacent pair of the wiring lines is increased in inverse proportion to the decrease of the wiring distance.
However, at the level of the integration density based on the conventional semiconductor technology, the line-to-line capacity as well as the line-to-substrate capacity was not so large as to be seriously questioned. However, it becomes necessary to solve the problem on power consumption caused by the recent extreme increase of the line-to-line capacity with elevation of the integration density.
Lastly, a conventional technique concerning parallel processing will be stated as follows.
A parallel processing has been used for mainly increasing the processing speed by processing a plural of units in parallel instead of processing one large complicated machine. In the conventional technique, communication between parallel elements such as parallel processors is executed by wiring system, since wiring lines for communication between the elements are comparatively few.
However, power consumption in a semiconductor device has rapidly increased and temperature rising in the device excess the limit temperature by recent progress in integration density of semiconductor elements. In order to solve the above thermal problem and speed up the processing of the device, the parallel elements are divided into smaller elements and increased in number.
Then, new problems of parallel processing software and communication speed between the elements have arisen. With respect to the problem on the parallel processing software, the possibility of improvement still remains. However, it is very difficult to solve the problem on the communication between parallel elements because the communication speed is still left as a fatal problem. Accordingly, it is very difficult to realize high speed communication by a parallel processor in the conventional wiring system.
As stated above, the power consumption of the semiconductor devices is extremely enlarged because of the increase of the integration degree in semiconductor devices achieved by the advance of fine-processing technology to the devices or of the increase of the operating frequency such as clock frequency fc caused by demand of improving the processing speed and the operating characteristics.
Moreover, the circuit construction of semiconductor devices becomes very complicated with an increase of the integration. Accordingly, the conventional semiconductor devices are likely to be in an abnormal state or get in trouble.